1. Field
The following description relates to an Electro-Static Discharge (ESD) protection device, and, for example, to an ESD protection device protecting an internal circuit from an ESD stress current.
2. Description of the Related Art
Generally, an ESD protection circuit is disposed between an internal circuit and an input pad, an output pad, an electric power pad, and a ground pad of a semiconductor device for preventing the internal circuit from being damaged by an ESD stress current that flows into the semiconductor device from a charged human body or machinery.
Depending on a degree of integration according to a system on chip, an area that the ESD protection device occupies accounts for a large proportion for determining an entire size of a semiconductor chip. In addition, since the ESD protection circuit serves as an important factor to determine the performance of chips, the ESD protection circuit is becoming increasingly important.
In many cases, the ESD protection device uses a Gate Grounded N-type Metal Oxide Semiconductor (GGNMOS) field effect transistor of which a gate, a source, and a bulk are formed in one connection and then the one connection is connected to a ground voltage node of Vss. A ground line Vss and an electric power line Vdd are connected to the source and a drain via contacts, respectively. At this time, normally, the contacts are arranged within the drain and source areas, and silicides are formed around the contacts to decrease a contact resistance.
As there is a desire for the shrinking of a semiconductor chip, when the electric power line and the ground line are arranged over the GGNMOS for reducing an area on which the electric power line and the ground line are formed, the contacts are arranged only at some areas of the source and drain, and the silicide are formed around the contacts, current paths are formed only between the contacts which face each other and have a minimum distance.
Accordingly, since the ESD stress current is concentrated on a specific contact so that the ESD protection device is easily destroyed, the ESD stress current does not smoothly discharge from the semiconductor chip. Therefore, the level of the ESD protection device is lowered.